Design of Energy-efficient Full Adder Using Hybrid-cmos Logic Style

Consider the CMOS SR flip-flop in the figure below. The circuit is fabricated in a 0.13um

CMOS process for which 1, Car = 44, Car

=430uA/V?, V.m = V, =0.4V , 1 = 0,y = 0 and

VDD=1.2V. Assume there are no short channel effects. The inverters have

(W/L)n=0.2um/0.13um and (W/L)p=0.8um/0.13um. The four NMOS transistors in the set-reset

circuit have equal (W/L) ratios. Find the minimum value required for this ratio to ensure the flip.

flop will switch.

Skills: Engineering, Electronics, Electrical Engineering, Circuit Design, Digital Electronics

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Design of Energy-efficient Full Adder Using Hybrid-cmos Logic Style

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